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| ds07-16701-1ea fujitsu microelectronics data sheet copyright?2005-2008 fujitsu microelect ronics limited all rights reserved 2005.3 32-bit microcontroller cmos fr60 mb91319 series mb91f318a/fv319a description the mb91319 series is the microcontrollers which use a high-performance 32-bit risc-cpu and contains various types of i/o resources for the embedded control that re quires high-performance and high-speed cpu processing. it is suitable for the embedded control in tv or pdp, requiring high-performance cpu processing power. this product is one of the fr60 family based on the fr 30/40 family cpu with enhanced bus access. it is applicable to faster-speed application. feature ? fr cpu ? 32-bit risc, load/store architecture with a five-stage pipeline ? operating frequency : 40 mhz (use of pll : oscillation 10 mhz) ? 16-bit fixed length instructions (basic instructions) , 1 instruction per cycle ? memory-to-memory transfer, bit manipulation, instruction for barrel shift etc. : instruction set optimized for embedded applications ? function entry/exit instructions, mult iple-register load/store instructions : instructions adapted for high-level languages ? register interlock functions: facilitating coding in assemblers (continued) pac k ag e 176-pin plastic lqfp (fpt-176p-m07)
mb91319 series 2 ? built-in multiplier with instruction-level support 32-bit multiplication with sign : 5 cycles 16-bit multiplication with sign : 3 cycles ? interrupt (pc, ps save) : 6 cycles, 16 priority levels ? harvard architecture allowing program access and data access to be executed simultaneously ? instruction prefetch function implemented by a four-word queue in the cpu ? instruction compatible with fr family ? bus interface this bus interface is used for internal macro if (usb, osdc) ?cs1 , cs2 , and cs3 areas are connected as following : cs1 area : reserved, cs2 area : usb function, cs3 area : osdc ? internal memory ? dmac (dma controller) ? 5 channels (ch0 and ch1 are connected to usb function. ) ? two forwarding factors (internal peripheral/software) ? specifying of addressing mode 32-bit full address (increased/decreased/fixed) ? transfer modes (demand transfer, burst transfer, step transfer, block transfer) ? selectable transfer data size : 8, 16, or 32-bit ? bit search module (for realos) ? search for the position of the bit ?1?/?0?-changed first in one word from the msb ? reload timer (including a channel for realos) ? 16-bit timer: 3 channels ? the internal clock is selectable from 2/8/32 divisions. ? uart ? full duplex double buffer ? 5 channels ? selectable parity on/off ? asynchronous (start-stop synchronized) or clk-synchronous communications selectable ? internal timer for dedicated baud rate ? external clock can be used as transfer clock. ? assorted error detection functions (for parity, frame, and overrun errors) (continued) memory mb91fv319a mb91f318a ram 64 kb 48 kb flash (for program) 1 mb 1 mb memory for font 512 kb flash 384 kb mask rom mb91319 series 3 ? i 2 c interface * ? 4 channels (built-in bridge function) ? master/slave sending and receiving ? clock synchronization function ? detecting transmitting direction function ? bus error detection function ? standard mode (max 100 kbps) /high speed mode (max 400 kbps) supported ? built-in fifo function with 16-byte data each for transmit/receive ? arbitration function ? slave address and general call address detection function ? start condition repeated generation and detection ? 10-bit/7-bit slave address ? interrupt controller ? total of external interrupt is 5. (one non-maskable interrupt pin (nmi ) and four normal interrupt pins (int3 to int0) ) ? interrupt from internal peripheral ? programmable priorities (16 levels) for all interrupts except the non-maskable interrupt ? at the stop, available use for wake up ? a/d converter ? 10-bit resolution, 10 channels ? serial compared conversion type : conversion time : approx. 10 s ? conversion mode (single conversion mode, scan conversion mode) ? start-up factor (software/external trigger) ? ppg ? 4 channels are incorporated. ? 16-bit down counter, 16-bit data register with buffer for setting cycles ? the internal clock is selectable from 1/4/16/64 divisions. ? pwc ? 1 channel (1 input) is incorporated. ? 16-bit up counter ? easy digital low pass filter ? multi function timer ? 4 channels are incorporated. ? low pass filter eliminating noise below the clock setting ? capable of pulse width measurement according to fine settings using seven types of clock signals ? event count function from pin input ? interval timer function using seven kinds of clock and external input clock ? usb function ? full speed ? double buffer of usb2.0 version ? control in/out, bulk in/out, interrupt in (continued) mb91319 series 4 (continued) ? osdc function ? rgb: each 3 bits (16 colors available among 512 colors) analog rgb output: max 50 mhz digital rgb output: max 90 mhz a font in 24 32 dots can be displayed up to 80 32. two-layered display of main/cc (font in cc layer is fixed at 18 dots in horizontal axis) 4096 characters at the maximum (including 16 characters for font ram) ? closed caption decoder function 2 channels are incorporated. cc decode function id-1 (480i/480p) decode function ? pll for video clock 3 plls generating dot clock and vbi clock ? other interval timer 16-bit timer : 3 channels watchdog timer ? i/o port max 88 ports ? other features built-in oscillation circuit as clock source init is prepared as a reset pin. watchdog timer reset and software reset are also available. stop mode and sleep mode are supported as low-power consumption mode. gear function built-in timebase timer package : lqfp-176, 0.5mm pitch, 24 mm 24 mm cmos technology : 0.25 m (eva, flash) power supply voltage : 3.3 v 0.3 v, 2.5 v 0.2 v 2-power supply * : ?purchase of fujitsu i 2 c components conveys a lic ense under the philips i 2 c patent rights to use these com- ponents in an i 2 c system provided that the system conforms to the i 2 c standard specification as defined by philips.? mb91319 series 5 pin assignment 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 140 139 138 137 136 135 134 133 37 38 39 40 41 42 43 44 96 95 94 93 92 91 90 89 81 82 83 84 85 86 87 88 hsync1 hsync2 hsync3 vdde vss vgs1/vci1 cpo1 vssp1 vddp1 vgs2/vci2 cpo2 vssp2 vddp2 vgs3/vci3 cpo3 vssp3 vddp3 vddr vref vr0 rout vssr vddg gout vssg vddb bout vssb vin0 vin1 vddis vsss vddi avcc avrh avss/avrl pc0/an0 pc1/an1 pc2/an2 pc3/an3 pc4/an4 pc5/an5 pc6/an6 pc7/an7 p02/sck4/tin2 p01/so4/tin1 p00/si4/tin0 p74 p73 p72 p71 p70 vdde vss vddi p57 p56 p55 p54 p53 p52/sck3 p51/so3 p50/si3 p47/scl2 p46/so2 p45/si2 p44/sda4 p43/sda3 p42/scl4 p41/scl3 p40/sda2 p37/scl2 p36/trg3 p35/trg2 p34/trg1 p33/trg0 nmi pa2/int3 pa1/int2 pa0/int1 vddi x1a vss x0a vdde p97/int0 p96/tmi3 p95/tmi2 vsync dcki dcko fh vob1 vob2 vddi r2 r1 r0 g2 g1 g0 b2 b1 b0 udp udm vdde x0b vss x1b vddi pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 p17 p16/atrg p15/ppg3 p14/ppg2 p13/ppg1 p12/ppg0 p11/tmo3 p10/tmo2 p07/tmo1 p06/tmo0 p05/to2 p04/to1 p03/to0 p94/tmi1 p93/tmi0 p92/rin p91/sck1 p90/so1 p87/si1 p86/sck0 p85/so0 p84/si0 p83/sda1 p82/scl1 p81/sda0 p80/scl0 init md3 md2 md1 md0 icd3 icd2 icd1 icd0 ics2 ics1 ics0 ibreak iclk trst vddi x1 vss x0 vdde p32 p31 p30 p27 p26 p25 p24 p23 p22 p21/an9 p20/an8 (fpt-176p-m07) (top view) mb91319 series 6 pin description (continued) pin no. pin name circuit type function 1 hsync1 g vertical synchronous input 1 2 hsync2 g vertical synchronous input 2 3 hsync3 g vertical synchronous input 3 4vdde ? i/o power supply 5 vss ? ground 6vgs1/vci1 ? guard band ground 7 cpo1 k charge pump output 8 vssp1 ? dot clock pll ground 9 vddp1 ? dot clock pll power supply 10 vgs2/vci2 ? guard band ground 11 cpo2 k charge pump output 12 vssp2 ? dot clock pll ground 13 vddp2 ? dot clock pll power supply 14 vgs3/vci3 ? guard band ground 15 cpo3 k charge pump output 16 vssp3 ? dot clock pll ground 17 vddp3 ? dot clock pll power supply 18 vddr ? d/a power supply for r 19 vref (1.1 v) k power supply reference input 20 vr0 (2.7 k ) k resistor connection pin 21 rout k r output (analog) 22 vssr ? d/a ground for r 23 vddg ? d/a power supply for g 24 gout k g output (analog) 25 vssg ? d/a ground for g 26 vddb ? d/a power supply for b 27 bout k b output (analog) 28 vssb ? d/a ground for b 29 vin0 k data slicer input 0 30 vin1 k data slicer input 1 31 vddis ? data slicer power supply 32 vsss ? data slicer ground 33 vddi ? internal logic power supply 34 avcc ? a/d power supply 35 avrh ? a/d reference power supply mb91319 series 7 (continued) pin no. pin name circuit type function 36 avss/avrl ? a/d ground 37 pc0 e general-purpose port an0 analog input 38 pc1 e general-purpose port an1 analog input 40 pc3 e general-purpose port an3 analog input 41 pc4 e general-purpose port an4 analog input 42 pc5 e general-purpose port an5 analog input 43 pc6 e general-purpose port an6 analog input 44 pc7 e general-purpose port an7 analog input 45 p20 e general-purpose port an8 analog input 46 p21 e general-purpose port an9 analog input 47 p22 c general-purpose port 48 p23 c general-purpose port 49 p24 c general-purpose port 50 p25 c general-purpose port 51 p26 c general-purpose port 52 p27 c general-purpose port 53 p30 c general-purpose port 54 p31 c general-purpose port 55 p32 c general-purpose port 56 vdde ? 3.3 v power supply 57 x0 a 10 mhz oscillation pin 58 vss ? ground 59 x1 a 10 mhz oscillation pin 60 vddi ? internal logic power supply 61 trst b dsu tool reset (in mb91f318a, this pin is the open pin so do not connect with other pins.) mb91319 series 8 (continued) pin no. pin name circuit type function 62 iclk m dsu clock (in mb91f318a, this pin is the open pin so do not connect with other pins.) 63 ibreak l dsu break (in mb91f318a, this pin is the open pin so do not connect with other pins.) 64 ics0 o dsu status (in mb91f318a, this pin is the open pin so do not connect with other pins.) 65 ics1 o dsu status (in mb91f318a, this pin is the open pin so do not connect with other pins.) 66 ics2 o dsu status (in mb91f318a, this pin is the open pin so do not connect with other pins.) 67 icd0 p dsu data (in mb91f318a, this pin is the open pin so do not connect with other pins.) 68 icd1 p dsu data (in mb91f318a, this pin is the open pin so do not connect with other pins.) 69 icd2 p dsu data (in mb91f318a, this pin is the open pin so do not connect with other pins.) 70 icd3 p dsu data (in mb91f318a, this pin is the open pin so do not connect with other pins.) 71 md0 f mode pin 72 md1 f mode pin 73 md2 f mode pin 74 md3 l mode pin 75 init b initial (reset) pin 76 p80 j general-purpose port scl0 i 2 c clock pin 77 p81 j general-purpose port sda0 i 2 c data pin 78 p82 j general-purpose port scl1 i 2 c clock pin 79 p83 j general-purpose port sda1 i 2 c data pin 80 p84 c general-purpose port si0 uart0 serial input 81 p85 c general-purpose port so0 uart0 serial output 82 p86 c general-purpose port sck0 uart0 clock input/output mb91319 series 9 (continued) pin no. pin name circuit type function 83 p87 c general-purpose port si1 uart1 serial input 84 p90 c general-purpose port so1 uart1 serial output 85 p91 c general-purpose port sck1 uart1 clock input/output 86 p92 c general-purpose port rin pwc input 87 p93 c general-purpose port tmi0 multi-functional timer 0 input 88 p94 c general-purpose port tmi1 multi-functional timer 1 input 89 p95 c general-purpose port tmi2 multi-functional timer 2 input 90 p96 c general-purpose port tmi3 multi-functional timer 3 input 91 p97 o general-purpose port int0 external interrupt input 0 92 vdde ? 3.3 v power supply 93 x0a a 32 khz oscillation pin 94 vss ? ground 95 x1a a 32 khz oscillation pin 96 vddi ? internal logic power supply 97 pa0 o general-purpose port int1 external interrupt input 1 98 pa1 o general-purpose port int2 external interrupt input 2 99 pa2 o general-purpose port int3 external interrupt input 3 100 nmi bnmi input 101 p33 c general-purpose port trg0 ppg0 trigger input 102 p34 c general-purpose port trg1 ppg1 trigger input mb91319 series 10 (continued) pin no. pin name circuit type function 103 p35 c general-purpose port trg2 ppg2 trigger input 104 p36 c general-purpose port trg3 ppg3 trigger input 105 p37 n general-purpose port scl2 i 2 c clock pin 106 p40 n general-purpose port sda2 i 2 c data pin 107 p41 n general-purpose port scl3 i 2 c clock pin 108 p42 n general-purpose port scl4 i 2 c clock pin 109 p43 n general-purpose port sda3 i 2 c data pin 110 p44 n general-purpose port sda4 i 2 c data pin 111 p45 c general-purpose port si2 uart2 serial input 112 p46 c general-purpose port so2 uart2 serial output 113 p47 c general-purpose port sck2 uart2 clock output 114 p50 c general-purpose port si3 uart3 serial input 115 p51 c general-purpose port so3 uart3 serial output 116 p52 c general-purpose port sck3 uart3 clock output 117 p53 c general-purpose port 118 p54 c general-purpose port 119 p55 c general-purpose port 120 p56 c general-purpose port 121 p57 c general-purpose port 122 vddi ? internal logic power supply 123 vss ? ground mb91319 series 11 (continued) pin no. pin name circuit type function 124 vdde ? 3.3 v power supply 125 p70 c general-purpose port 126 p71 c general-purpose port 127 p72 c general-purpose port 128 p73 c general-purpose port 129 p74 c general-purpose port 130 p00 c general-purpose port si4 uart4 serial input tin0 reload timer 0 trigger input 131 p01 c general-purpose port so4 uart4 serial output tin1 reload timer 1 trigger input 132 p02 c general-purpose port sck4 uart4 clock input tin2 reload timer 2 trigger input 133 p03 c general-purpose port to0 reload timer 0 output 134 p04 c general-purpose port to1 reload timer 1 output 135 p05 c general-purpose port to2 reload timer 2 output 136 p06 c general-purpose port tmo0 multi-functional timer 0 output 137 p07 c general-purpose port tmo1 multi-functional timer 1 output 138 p10 c general-purpose port tmo2 multi-functional timer 2 output 139 p11 c general-purpose port tmo3 multi-functional timer 3 output 140 p12 c general-purpose port ppg0 ppg0 output 141 p13 c general-purpose port ppg1 ppg1 output 142 p14 c general-purpose port ppg2 ppg2 output mb91319 series 12 (continued) pin no. pin name circuit type function 143 p15 c general-purpose port ppg3 ppg3 output 144 p16 c general-purpose port atrg a/d conversion trigger input 145 p17 c general-purpose port 146 pb0 c general-purpose port 147 pb1 c general-purpose port 148 pb2 i general-purpose port 149 pb3 c general-purpose port 150 pb4 c general-purpose port 151 pb5 c general-purpose port 152 pb6 h general-purpose port 153 pb7 c general-purpose port 154 vddi ? internal power supply 155 x1b a 48 mhz oscillation pin 156 vss ? ground 157 x0b a 48 mhz oscillation pin 158 vdde ? 3.3 v power supply 159 udm usb usb function 160 udp usb function 161 b0 d rgb digital output 162 b1 d rgb digital output 163 b2 d rgb digital output 164 g0 d rgb digital output 165 g1 d rgb digital output 166 g2 d rgb digital output 167 r0 d rgb digital output 168 r1 d rgb digital output 169 r2 d rgb digital output 170 vddi ? internal logic power supply 171 vob2 d translucent color period output 172 vob1 d osd display period output 173 fh d horizontal synchronous output 174 dcko d dot clock output 175 dcki g dot clock input 176 vsync g vertical synchronous output mb91319 series 13 i/o circuit type (continued) type circuit type remarks a oscillation circuit b ? cmos level hysteresis input ? with pull-up resistor c ? cmos level output ? cmos level hysteresis input ? with standby control x1 x0 clock input standby control digital input digital input digital output digital output standby control mb91319 series 14 (continued) type circuit type remarks d ? 2.5 v cmos level output ? cmos level hysteresis input ? with standby control e ? cmos level output ? cmos level hysteresis input ? with standby control ? with analog input switch f ? cmos level input ? without standby control 2.5 v digital input digital output digital output standby control digital input digital output digital output analog input control standby control digital input mb91319 series 15 (continued) type circuit type remarks g ? cmos level hysteresis input ? without standby control h ? cmos level output ? cmos level hysteresis input ? with standby control ? with pull-down resistor i ? cmos level output ? cmos level hysteresis input ? with standby control ? with pull-up resistor digital input digital input digital output digital output standby control pull-down control digital input digital output digital output standby control mb91319 series 16 (continued) type circuit type remarks j ? open drain output ? cmos level hysteresis input ? with standby control k analog pin l ? cmos level hysteresis input ? with pull-down resistor m cmos level output digital input digital output open drain control standby control digital input digital output digital output analog input or analog output mb91319 series 17 (continued) type circuit type remarks n ?3 ports for i 2 c ? cmos level hysteresis input ? cmos level output ? with stop control o ? cmos level output ? cmos level hysteresis input ? without standby control digital input digital output open drain control digital input open drain control digital output digital input digital output open drain control } control control digital input digital output digital output mb91319 series 18 (continued) type circuit type remarks p ? cmos level output ? cmos level hysteresis input ? without standby control ? with pull-down resistor digital input digital output digital output mb91319 series 19 handling devices ? preventing latchup latch-up may occur in a cmos ic if a voltage greater than v cc or less than v ss is applied to an input or output pin or if an above-rating voltage is applied between v cc and v ss pins. a latchup, if it o ccurs, significan tly increases the power supply current and may cause thermal destruction of an element. when you use a cmos ic, be very careful not to exceed the maximum rating. ? treatment of unused input pins do not leave an unused input pin open, since it may cause a malfunction. handle by, for example, using a pull- up or pull-down resistor. ? power supply pins in products with multiple v cc or v ss pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. however, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with the v cc and v ss pins of this device at the low impedance. it is also advisable to connect a ce ramic capacitor of approximately 0.1 f as a bypass capacitor between v cc and v ss pins near this device. ? crystal oscillator circuit noise near the x0 and x1 pins may cause the device to malfunction. design the printed circuit board so that x0, x1, the crystal oscillator (or cerami c oscillator) , and the bypass capacito r to ground are located as close to the device as possible. it is strongly recommended to design the pc board artwork with the x0 and x1 pins surrounded by ground plane because stable operation can be expected with such a layout. ? mode pins (md0 to md3) these pins should be connected directly to v cc or v ss . to prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that the distance between the mode pins and v cc or v ss is as short as possible and the connection impedance is low. ? tool reset pins (trst ) when not using the tool, be sure to input the same signal as init to these pins. apply the same treatment to mass-produced products as well. ? operation at power-on be sure to execute setting in itialized reset (init) with init pin immediately after start-up. immediately after the power supply is turned on, hold the low level input to the init pin for the settling time required for the oscillator circuit to ta ke the oscillation stabilization wait ti me for the oscillator circuit. (for init via the init pin, the oscillation stabilization wait time setting is initialized to the minimum value.) ? oscillation input at power on when turning the power on, maintain cl ock input until the device is releas ed from the oscilla tion stabilization wait state. mb91319 series 20 ? notes on power-on/shut-down do not apply v dde (external) alone continuously (for over an indication of one minute) with v ddi (internal) disconnected not to cause a reliability problem with lsi. when v dde (external) returns from the off state to the on state, the circuit may fail to hold its internal state, for example, due to power supply noise. turn on/off the power supply in the following order: ? undefined output on power-on when the power is turned on, the output pin may remain unstable until the internal power supply becomes stable. ? clock about the attention when the external clock is used when the external clock is used, in principle, supply a clock signal to the x0 (x0a, x0b) pin and an opposite- phase clock signal to the x1 (x1a, x1 b) pin at the same time. however, in this case the st op mode (oscillator stop mode) must not be used (this is because, in stop mode, the x1 (x1a, x1b) pin stops at ?h? output) . at 12.5 mhz or less, the device can be used with the clock signal supplied only to the x0 (x0a, x0b) pin. note : the x1 (x1a, x1b) pin must be designed to have a delay within 15 ns, at 10 mhz, from the signal to the x0 (x0a, x0b) pin. ? at power-on v ddi (internal) analog v dde (external) signal ? turn off signal v dde (external) analog v ddi (internal) x0, x0a, x0b x1, x1a, x1b mb91fv319a/mb91f318a note: the stop mode (oscillati on stop mode) cannot be used. ? using an external clock (normal) x0, x1a, x1a x1, x1a, x1b open mb91fv319a/mb91f318a ? using an external clock (available at 12.5 mhz or less) mb91319 series 21 ? restrictions common in mb91319 series (1) clock control block take the oscillation stabilization wait ti me during low level input to the init pin. (2) bit search module the 0-detection data register (bsd0) , 1-detection data register (bsd1) , and transition-detection data register (bdsc) are only word-accessible. (3) i/o port ports are accessed only in bytes. (4) low-power consumption mode ? to enter the standby mode, use the synchronous standby mode (set with the syncs bit as bit 8 in the tbcr : timebase counter control register) and be sure to use the following sequence: in addition, set the i-flag and the ilm and icr registers to branch to an interrupt handler when the interrupt handler triggers the microcontroller to return from the standby mode. (5) notes on the ps register as the ps register is processed by some instructions in advance, exception handling below may cause the interrupt handling routine to break when the debugger is used or the display contents of flags in the ps register to be updated. as the microcontroller is designed to carry out reprocessing correctly upon returning from such an eit event, it performs operations before and after the eit as specified in either case. (ld1 #value_of_stanby, r0) (ld1 #_stcr, r12) stb r0, @r12 ; write to standby control register (stcr) ldub @r12, r0 ; stcr read for synchronous standby ldub @r12, r0 ; dummy re-read of stcr nop ; nop 5 for adjusted timing nop nop nop nop ? the following operations are performed when the instruction followed by a data event, when breaks when single-stepped, or when a divou/divos emulator menu instructionreceives a user interrupt or nmi. (1)the d0 and d1 flags are updated in advance. (2)an eit handling routine (user interrupt, nmi, or emulator) is executed. (3)upon returning from the eit, the divou/divos instruction is executed and the d0 and d1 flags are updated to the same values as in (1) . ? the following operations are performed when the orccr, stilm, mov ri, and ps instructions are executed to allow the interrupt at the state which a user interrupt/nmi cause occurs. (1)the ps register is updated in advance. (2)an eit handling routine (user interrupt and nmi) is executed. (3)upon returning from the eit, the above instructions are executed and the ps register is updated to the same value as in (1) . mb91319 series 22 (6) watchdog timer the watchdog timer built in this model monitors a program that it defers a reset within a certain period of time. the watchdog timer resets the cpu if the program runs out of controls, preventing the reset defer function from being executed. once the function of the watchdog timer is enabled, therefore, the watchdog timer keeps on operating programs until it resets the cpu. as an exception, the watchdog timer defers a reset automatically under the condition in which the cpu stops program execution. for those conditions to which this exception applies, see the function description of watchdog timer. a watchdog reset may not be generated in the above situation caused by the system running out of control. in that case, please reset (init) by external init pin. (7) notes on using a/d the mb91319 series contains an a/d converter. supply power to the avcc at 3.3 v. evaluation chip mb91fv319a specific (8) simultaneous generation of software break and user interrupt/nmi (only for mb91fv319a) if a software break and a user interrupt/nmi occur simultaneously, the emulator debugger may cause the following symptoms. ? the debugger stops pointing to a location other than the programmed breakpoints. ? the halted program is not re-executed correctly. if these phenomena occur, use a hardware break instead of the software break. if the monitor debugger has been used, avoid setting any break at the relevant location. (9) step execution of reti instruction in an environment where interrupts frequently occur during single-step execution, only the relevant interrupt processing routines are exec uted repeatedly during single -step execution of the re ti instruction. this will prevent the main routine and low-interrupt-level programs from being executed. to avoid it, do not single- step reti instructions. when the relevant interrupt routine no longer requires being debugged, disable the relevant interrupt and perform debugging. (10) about an operand break do not apply a data event break to access to the area containing the address of a stack pointer. (11) example of batch file for configuration to debug a program downloaded to internal ram, be sure to execute the following batch file after executing reset. #---------------------------------------------------------------------------- #set modr (0x7fd) = enable in memory + 16-bit external bus set mem/byte 0x7fd = 0x5 #------------------------------------------------------------------------------ (12) address in the built-in flash/rom area (1 mb product) the address 0x0017fff8 in the built-in flash/rom area has been reserved. you must configure the fe. mb91319 series 23 block diagram osdc flash 1 mb ram 64 kb* 1 48 kb* 1 dmac 5 channels bus converter pwc 1 channel ppg 4 channels a/d 10 channels cc decoder 2 channels uart 5 channels i 2 c 4 channels 32 32 flash 512 kb* 2 rom 384 kb* 2 font flash bit search fr60 cpu core 32 to 16 adapter external i/f usb function reload timer 3 channels multi-function 4 channels clock control interrupt controller external interrupt ports *1 : mb91fv319a contains the data ram of 64kb, and mb91f318a contains that of 48kb. *2 : mb91fv319a contains the font rom of 512kb flash memory, and mb91f318a contains that of 384kb mask rom. mb91319 series 24 memory space the fr family has 4 gb of logical address space (2 32 addresses) available to the cpu by linear access. ? direct addressing areas the following address space areas are used as i/o areas. these areas are called direct addressing areas, in whic h the address of an operand can be specified directly during an instruction. the size of directly addressable areas depends on the length of the data being accessed as shown below. ? memory map byte data access : 000 h to 0ff h half word data access : 000 h to 1ff h word data access : 000 h to 3ff h 0000 0000 h 0000 0400 h 0001 0000 h 0003 c000 h 0002 f800 h 0004 0000 h 0005 0000 h 0006 0000 h 0007 0000 h 0008 0000 h 0018 0000 h 0020 0000 h ffff ffff h 512 kb * 2 i/o i/o flashrom1 1 mb flashrom2 osdc *1 : built-in ram area of mb91f318a is 0003 4000 h to 0003 ffff h (48 kb) . *2 : mb91f318a single-chip mode access disallowed access disallowed access disallowed font ram built-in ram* 1 usb function access disallowed mb91319 series 25 i/o map this shows the correspondence between the memory space area and various peripheral resource registers. [how to read the table] note : initial values of register bits are represented as follows : ?1? : initial value ?1? ?0? : initial value ?0? ?x? : initial value ?x? ? - ? : no physical register at this location (continued) address register block + 0 + 1 + 2 + 3 000000 h to 00000f h ???? reserved 000010 h pdr0[r/w] xxxxxxxx pdr1[r/w] xxxxxxxx pdr2[r/w] xxxxxxxx pdr3[r/w] xxxxxxxx r-bus port data register 000014 h pdr4[r/w] xxxxxxxx pdr5[r/w] xxxxxxxx ? pdr7[r/w] --xxxxxx 000018 h pdr8[r/w] xxxxxxxx pdr9[r/w] xxxxxxxx pdra[r/w] -----xxx pdrb[r/w] xxxxxxxx 00001c h pdrc[r/w] xxxxxxxx ??? 000020 h adcth[r/w] xxxxxx00 adctl[r/w] 00000x00 adch[r/w] 00000000 00000000 10-bit a/d converter 000024 h adat0[r] xxxxxx00 00000000 adat1[r] xxxxxx00 00000000 000028 h adat2[r] xxxxxx00 00000000 adat3[r] xxxxxx00 00000000 00002c h adat4[r] xxxxxx00 00000000 adat5[r] xxxxxx00 00000000 000030 h adat6[r] xxxxxx00 00000000 adat7[r] xxxxxx00 00000000 address register block + 0 + 1 + 2 + 3 00000000 h pdr0 [r/w] xxxxxxxx pdr1 [r/w] xxxxxxxx pdr2 [r/w] xxxxxxxx pdr3 [r/w] xxxxxxxx t-unit port data register read/write attribute initial value of register after a reset register name (first-column register at address 4n; second-column register at address 4n + 2) leftmost register address (for word-length access, column 1 of the register becomes the msb of the data.) mb91319 series 26 (continued) address register block + 0 + 1 + 2 + 3 000034 h ???? reserved 000038 h ???? 00003c h ???? 000040 h eirr [r/w] 00000000 enir [r/w] 00000000 elvr [r/w] 00000000 ext int 000044 h dicr [r/w] -------0 hrcl [r/w] 0--11111 ? dlyi/i-unit 000048 h tmrlr0 [w] xxxxxxxx xxxxxxxx tmr0 [r] xxxxxxxx xxxxxxxx reload timer 0 00004c h ? tmcsr0 [r/w] ----0000 00000000 000050 h tmrlr1 [w] xxxxxxxx xxxxxxxx tmr1 [r] xxxxxxxx xxxxxxxx reload timer 1 000054 h ? tmcsr1 [r/w] ----0000 00000000 000058 h tmrlr2 [w] xxxxxxxx xxxxxxxx tmr2 [r] xxxxxxxx xxxxxxxx reload timer 2 00005c h ? tmcsr2 [r/w] ----0000 00000000 000060 h ssr0 [r/w] 00001-00 sidr0 [r/w] xxxxxxxx scr0 [r/w] 00000100 smr0 [r/w] 00--0-0- uart0 000064 h utim0 [r] (utimr [w]) 00000000 00000000 drcl0 [w] -------- utimc0 [r/w] 0--00001 u-timer 0 000068 h ssr1 [r/w] 00001-00 sidr1 [r/w] xxxxxxxx scr1 [r/w] 00000100 smr1 [r/w] 00--0-0- uart1 00006c h utim1 [r] (utimr [w]) 00000000 00000000 drcl1 [w] -------- utimc1 [r/w] 0--00001 u-timer 1 000070 h ssr2 [r/w] 00001-00 sidr2 [r/w] xxxxxxxx scr2 [r/w] 00000100 smr2 [r/w] 00--0-0- uart2 000074 h utim2 [r] (utimr [w]) 00000000 00000000 drcl2 [w] -------- utimc2 [r/w] 0--00001 u-timer 2 000078 h ssr3 [r/w] 00001-00 sidr3 [r/w] xxxxxxxx scr3 [r/w] 00000100 smr3 [r/w] 00--0-0- uart3 00007c h utim3 [r] (utimr [w]) 00000000 00000000 drcl3 [w] -------- utimc3 [r/w] 0--00001 u-timer 3 000080 h ssr4 [r/w] 00001-00 sidr4 [r/w] xxxxxxxx scr4 [r/w] 00000100 smr4 [r/w] 00--0-0- uart4 000084 h utim4 [r] (utimr [w]) 00000000 00000000 drcl4 [w] -------- utimc4 [r/w] 0--00001 u-timer 4 mb91319 series 27 (continued) address register block + 0 + 1 + 2 + 3 000088 h ?? reserved 00008c h ?? 000090 h pwccl[r/w] 0000--00 pwcch[r/w] 00-00000 ? pwc 000094 h pwcd[r] xxxxxxxx xxxxxxxx ? 000098 h pwcc2[r/w] 000----- reserved ? pwc 00009c h pwcud[r] xxxxxxxx xxxxxxxx ? 0000a0 h ?? reserved 0000a4 h ?? 0000a8 h ?? 0000ac h ?? 0000b0 h ifn0 [r] 00000000 ifrn0 [r/w] 00000000 ifcr0 [r/w] 00-00000 ifdr0 [r/w] 00000000 i 2 c interface 0 0000b4 h ibcr0 [r/w] 00000000 ibsr0 [r/w] 00000000 itba0 [r/w] ------00 00000000 0000b8 h itmk0 [r/w] 00----11 11111111 ismk0 [r/w] 01111111 isba0 [r/w] 00000000 0000bc h ? idar0 [r/w] 00000000 iccr0 [r/w] 0-011111 idbl0 [r/w] -------0 0000c0 h ifn1 [r] 00000000 ifrn1 [r/w] 00000000 ifcr1 [r/w] 00-00000 ifdr1 [r/w] 00000000 i 2 c interface 1 0000c4 h ibcr1 [r/w] 00000000 ibsr1 [r/w] 00000000 itba1 [r/w] ------00 00000000 0000c8 h itmk1 [r/w] 00----11 11111111 ismk1 [r/w] 01111111 isba1 [r/w] 00000000 0000cc h ? idar1 [r/w] 00000000 iccr1 [r/w] 0-011111 idbl1 [r/w] -------0 0000d0 h ifn2 [r] 00000000 ifrn2 [r/w] 00000000 ifcr2 [r/w] 00-00000 ifdr2 [r/w] 00000000 i 2 c interface 2 0000d4 h ibcr2 [r/w] 00000000 ibsr2 [r/w] 00000000 itba2 [r/w] ------00 00000000 0000d8 h itmk2 [r/w] 00----11 11111111 ismk2 [r/w] 01111111 isba2 [r/w] 00000000 0000dc h ? idar2 [r/w] 00000000 iccr2 [r/w] 0-011111 idbl2 [r/w] -------0 mb91319 series 28 (continued) address register block + 0 + 1 + 2 + 3 0000e0 h ifn3 [r] 00000000 ifrn3 [r/w] 00000000 ifcr3 [r/w] 00-00000 ifdr3 [r/w] 00000000 i 2 c interface 3 0000e4 h ibcr3 [r/w] 00000000 ibsr3 [r/w] 00000000 itba3 [r/w] ------00 00000000 0000e8 h itmk3 [r/w] 00----11 11111111 ismk3 [r/w] 01111111 isba3 [r/w] 00000000 0000ec h ? idar3 [r/w] 00000000 iccr3 [r/w] 0-011111 idbl3 [r/w] -------0 0000f0 h t0lpcr [r/w] -----000 t0ccr [r/w] 0-010000 t0tcr [r/w] 00000000 t0r [r/w] ---00000 multi-functional timer 0000f4 h t0drr [r/w] xxxxxxxx xxxxxxxx t0crr [r/w] xxxxxxxx xxxxxxxx 0000f8 h t1lpcr [r/w] -----000 t1ccr [r/w] 0-000000 t1tcr[r/w] 00000000 t1r [r/w] ---00000 0000fc h t1drr [r/w] xxxxxxxx xxxxxxxx t1crr [r/w] xxxxxxxx xxxxxxxx 000100 h t2lpcr [r/w] -----000 t2ccr [r/w] 0-000000 t2tcr [r/w] 00000000 t2r [r/w] ---00000 000104 h t2drr [r/w] xxxxxxxx xxxxxxxx t2crr [r/w] xxxxxxxx xxxxxxxx 000108 h t3lpcr [r/w] -----000 t3ccr [r/w] 0-000000 t3tcr [r/w] 00000000 t3r [r/w] ---00000 00010c h t3drr [r/w] xxxxxxxx xxxxxxxx t3crr [r/w] xxxxxxxx xxxxxxxx 000110 h tmode [r/w] -------- -----0-- ?? 000114 h to 00011f h ?? reserved 000120 h ptmr0 [r] 11111111 11111111 pcsr0 [w] xxxxxxxx xxxxxxxx ppg0 000124 h pdut0 [w] xxxxxxxx xxxxxxxx pcnh0 [r/w] 00000000 pcnl0 [r/w] 00000000 000128 h ptmr1 [r] 11111111 11111111 pcsr1 [w] xxxxxxxx xxxxxxxx ppg1 00012c h pdut1 [w] xxxxxxxx xxxxxxxx pcnh1 [r/w] 00000000 pcnl1 [r/w] 00000000 000130 h ptmr2 [r] 11111111 11111111 pcsr2 [w] xxxxxxxx xxxxxxxx ppg2 000134 h pdut2 [w] xxxxxxxx xxxxxxxx pcnh2 [r/w] 00000000 pcnl2 [r/w] 00000000 mb91319 series 29 (continued) address register block + 0 + 1 + 2 + 3 000138 h ptmr3 [r] 11111111 11111111 pcsr3[w] xxxxxxxx xxxxxxxx ppg3 00013c h pdut3 [w] xxxxxxxx xxxxxxxx pcnh3 [r/w] 00000000 pcnl3 [r/w] 00000000 000140 h to 00014c h ? reserved 000150 h to 00015c h ? reserved 000160 h dslc00 0------- dslc10 -011---- ccdc0 00-00011 vsep0 00--0001 ccd slicer 0 channel 000164 h csysep0 -101-011 hmask0 --100000 hclr0 ---00110 fld0 00100000 000168 h hcnt0 00000000 c21h0 0-111111 crip0 11111111 cric0 000-0000 00016c h cstb0 11111111 cdth0 11111111 cdat00 00000000 cdat10 00000000 000170 h id1c0 0-----00 id20h0 0-111111 idref0 0-111111 idth0 11111111 000174 h idstb0 11111111 iddat00 --000000 iddat10 00000000 iddat20 --000000 000178 h dsac10 ---000-0 dsac20 10110011 dsac30 00-00-00 ? 00017c h ???? 000180 h dslc01 0------- dslc11 -011---- ccdc1 00-00011 vsep1 00--0001 ccd slicer 1 channel 000184 h csytsep1 -101-011 hmask1 --100000 hclr1 ---00110 fld1 00100000 000188 h hcnt1 00000000 c21h1 0-111111 crip1 11111111 cric1 000-0000 00018c h cstb1 11111111 cdth1 11111111 cdat01 00000000 cdat1 00000000 000190 h id1c1 0------00 id20h1 0-111111 idref1 0-111111 idth1 11111111 000194 h idstb1 11111111 iddat01 --000000 iddat11 00000000 iddat21 --000000 000198 h dsac11 ---000-0 dsac21 10110011 dsac31 00-00-00 ? 00019c h ???? mb91319 series 30 (continued) address register block + 0 + 1 + 2 + 3 0001a0 h to 0001fc h ? reserved 000200 h dmaca0 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx dmac 000204 h dmacb0 [r/w] 00000000 00000000 00000000 00000000 000208 h dmaca1 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 00020c h dmacb1 [r/w] 00000000 00000000 00000000 00000000 000210 h dmaca2 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx dmac 000214 h dmacb2 [r/w] 00000000 00000000 00000000 00000000 000218 h dmaca3 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 00021c h dmacb3 [r/w] 00000000 00000000 00000000 00000000 000220 h dmaca4 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 000224 h dmacb4 [r/w] 00000000 00000000 00000000 00000000 000228 h ? 00022c h to 00023c h ? reserved 000240 h dmacr [r/w] 0xx00000 xxxxxxxx xxxxxxxx xxxxxxxx dmac 000244 h to 0002fc h ? reserved 000300 h to 0003ec h ? 0003f0 h bsd0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx bit search module 0003f4 h bsd1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003f8 h bsdc [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003fc h bsrr [r] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx mb91319 series 31 (continued) address register block + 0 + 1 + 2 + 3 000400 h ddr0 [r/w] 00000000 ddr1 [r/w] 00000000 ddr2 [r/w] 00000000 ddr3 [r/w] 00000000 r-bus port direction register 000404 h ddr4 [r/w] 00000000 ddr5 [r/w] 00000000 ? ddr7 [r/w] --000000 000408 h ddr8 [r/w] 00000000 ddr9 [r/w] 00000000 ddra [r/w] -----000 ddrb [r/w] 00000000 00040c h ddrc [r/w] 00000000 ??? 000410 h pfr0 [r/w] 0--00000 pfr1 [r/w] 00000000 pfr2 [r/w] 00000000 pfr3 [r/w] 00000000 r-bus port function register 000414 h pfr4 [r/w] 0000--00 pfr5 [r/w] 11111111 pfr6 [r/w] 11111111 pfr7 [r/w] 11111111 000418 h pfr8 [r/w] 11111111 pfr9 [r/w] 11111111 pfra [r/w] 11111111 pfrb [r/w] 11111111 00041c h pfrc [r/w] 1111---1 pfrd [r/w] ---11111 ?? 000420 h to 00043c h ? reserved 000440 h icr00 [r/w] ---11111 icr01 [r/w] ---11111 icr02[r/w] ---11111 icr03 [r/w] ---11111 interrupt control unit 000444 h icr04 [r/w] ---11111 icr05 [r/w] ---11111 icr06 [r/w] ---11111 icr07 [r/w] ---11111 000448 h icr08 [r/w] ---11111 icr09 [r/w] ---11111 icr10 [r/w] ---11111 icr11 [r/w] ---11111 00044c h icr12 [r/w] ---11111 icr13 [r/w] ---11111 icr14 [r/w] ---11111 icr15 [r/w] ---11111 000450 h icr16 [r/w] ---11111 icr17 [r/w] ---11111 icr18 [r/w] ---11111 icr19 [r/w] ---11111 000454 h icr20 [r/w] ---11111 icr21 [r/w] ---11111 icr22 [r/w] ---11111 icr23 [r/w] ---11111 000458 h icr24 [r/w] ---11111 icr25 [r/w] ---11111 icr26 [r/w] ---11111 icr27 [r/w] ---11111 00045c h icr28 [r/w] ---11111 icr29 [r/w] ---11111 icr30 [r/w] ---11111 icr31 [r/w] ---11111 000460 h icr32 [r/w] ---11111 icr33 [r/w] ---11111 icr34 [r/w] ---11111 icr35 [r/w] ---11111 000464 h icr36 [r/w] ---11111 icr37 [r/w] ---11111 icr38 [r/w] ---11111 icr39 [r/w] ---11111 000468 h icr40 [r/w] ---11111 icr41 [r/w] ---11111 icr42 [r/w] ---11111 icr43 [r/w] ---11111 00046c h icr44 [r/w] ---11111 icr45 [r/w] ---11111 icr46 [r/w] ---11111 icr47 [r/w] ---11111 mb91319 series 32 (continued) address register block + 0 + 1 + 2 + 3 000470 h to 00047c h ? reserved 000480 h rsrr [r/w] 10000000* 2 stcr [r/w] 00110011* 2 tbcr [r/w] 00xxxx00* 1 ctbr [w] xxxxxxxx clock control unit 000484 h clkr [r/w] 00000000* 1 wpr [w] xxxxxxxx divr0 [r/w] 00000011* 1 divr1[r/w] 00000000* 1 000488 h ?? osccr [r/w] xxxxxxx0 ? reserved 00048c h wpcr [r/w] b 00---000 ??? watch timer 000490 h oscr [r/w] b 00---000 ??? main oscillation stabilization wait timer 000494 h to 0005fc h ? reserved 000600 h to 0007fc h ? reserved 000800 h to 000afc h ? reserved 000b00 h ests0 [r/w] x0000000 ests1 [r/w] xxxxxxxx ests2 [r] 1xxxxxxx ? dsu 000b04 h ectl0 [r/w] 0x000000 ectl1 [r/w] 00000000 ectl2 [w] 000x0000 ectl3 [r/w] 00x00x11 000b08 h ecnt0 [w] xxxxxxxx ecnt1 [w] xxxxxxxx eusa [w] xxx00000 edtc [w] 0000xxxx 000b0c h ewp1 [r] 00000000 00000000 ? 000b10 h edtr0 [w] xxxxxxxx xxxxxxxx edtr1 [w] xxxxxxxx xxxxxxxx 000b14 h to 000b1c h ? 000b20 h eia0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b24 h eia1 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx mb91319 series 33 (continued) address register block + 0 + 1 + 2 + 3 000b28 h eia2 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx dsu 000b2c h eia3 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b30 h eia4 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b34 h eia5 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b38 h eia6 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b3c h eia7 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b40 h edta [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b44 h edtm [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b48 h eoa0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b4c h eoa1 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b50 h epcr [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b54 h epsr [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b58 h eiam0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b5c h eiam1 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b60 h eoam0/eodm0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b64 h eoam1/eodm1 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b68 h eod0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b6c h eod1 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b70 h to 000ffc h ? reserved mb91319 series 34 (continued) *1 : the initial value of the register varies with the reset level. the initial value shown is the one after an init level reset. *2 : the initial value of the register varies with the reset level. the initial value shown is the one after an init level reset by the init pin. address register block + 0 + 1 + 2 + 3 001000 h dmasa0 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx dmac 001004 h dmada0 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001008 h dmasa1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00100c h dmada1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001010 h dmasa2 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001014 h dmada2 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001018 h dmasa3 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00101c h dmada3 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001020 h dmasa4 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001024 h dmada4 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001028 h to 006ffc h ? reserved 007000 h flcr [r/w] 0110x000 ? program flash i/f 007004 h flwc [r/w] 00010011 ? 007008 h to 0070ff h ? reserved 007100 h fncr [r/w] 0110x000 ? font flash i/f 007104 h fnwt [r/w] 00010011 ? mb91319 series 35 (continued) address register block + 0 + 1 + 2 + 3 050000 h to 050024 h reserved reserved 050028 h to 05ffff h reserved reserved 060000 h fifo0o [r] xxxxxxxx xxxxxxxx fifo0i [w] xxxxxxxx xxxxxxxx usb function 060004 h fifo1 [r] xxxxxxxx xxxxxxxx fifo2 [w] xxxxxxxx xxxxxxxx 060008 h fifo3 [r] xxxxxxxx xxxxxxxx ? 06000c h to 06001f h reserved 060020 h reserved cont1 [r/w] 000xx0xx xxx00000 060024 h cont2 [r/w] xxxxxxxx xxx00000 cont3 [r/w] xxxxxxxx xxx00000 060028 h cont4 [r/w] xxxxxxxx xxx00000 cont5 [r/w] xxxxxxxx xxxx00xx 06002c h cont6 [r/w] xxxxxxxx xxxx00xx cont7 [r/w] xxxxxxxx xxx00000 060030 h cont8 [r/w] xxxxxxxx xxx00000 cont9 [r/w] 0xx0xxxx 0xxx0000 060034 h cont10 [r/w] 00000000 x00000xx ttsize [r/w] 00010001 00010001 060038 h trsize [r/w] 00010001 00010001 reserved 06003c h reserved 060040 h rsize0 [r] xxxxxxxx xxxx0000 reserved 060044 h rsize1 [r] xxxxxxxx x0000000 reserved 060048 h to 06005f h reserved 060060 h reserved st1 [r/w] xxxxxx00 00000000 060064 h reserved mb91319 series 36 (continued) address register block + 0 + 1 + 2 + 3 060068 h st2 [r] xxxxxxxx x0000000 st3 [r/w] 00xxxxxx x0000000 usb function 06006c h st4 [r/w] xxxxx000 00000000 st5 [r/w] 0xx00xxx xx000000 060070 h to 06007f h reserved 060080 h to 06ffff h reserved reserved 078000 h osd_vadr [w] xxxxxxxx xxxxxxxx osd_cd1 [w] xxxxxxxx xxxxxxxx osdc (main) 078004 h osd_cd2 [w] xxxxxxxx xxxxxxxx osd_rcd1 [w] xxxxxxxx xxxxxxxx 078008 h osd_rcd2 [w] xxxxxxxx xxxxxxxx osd_soc1 [w] xxxxxxxx 0000xxxx 07800c h osd_soc2 [w] xxxxxxxx xxxxxxxx osd_vdpc [w] xxxxxxxx xxxxxxxx 078010 h osd_hdpc [w] xxxxxxxx xxxxxxxx osd_cvsc [w] xxxxxxxx xxxxxxxx 078014 h osd_sbfcc [w] xxxxxxxx xxxxxxxx osd_thcc [w] xxxxxxxx xxxxxxxx 078018 h osd_gfcc [w] xxxxxxxx xxxxxxxx osd_sbcc1 [w] xxxxxxxx xxxxxxxx 07801c h osd_sbcc2 [w] xxxxxxxx xxxxxxxx osd_spcc1 [w] xxxxxxxx xxxxxxxx 078020 h osd_spcc2 [w] xxxxxxxx xxxxxxxx osd_spcc3 [w] xxxxxxxx xxxxxxxx 078024 h osd_spcc4 [w] xxxxxxxx xxxxxxxx osd_syncc [w] xxxxxxxx xxxxxxxx 078028 h ?? 07802c h ? osd_ioc1 [w] xxxxxxxx xxxxxx00 078030 h osd_ioc2 [w] xxxxxxxx xxxxxxxx osd_dpc1 [w] xxxxxxxx xxxxxxxx 078034 h osd_dpc2 [w] xxxxxxxx xxxxxxxx osd_dpc3 [w] xxxxxxxx xxxxxxxx 078038 h osd_dpc4 [w] xxxxxxxx xxxxxxxx osd_irc [w] xxxxxxxx xxxxxxxx 07803c h osd_plt0 [w] xxxxxxxx xxxxxxxx osd_plt1 [w] xxxxxxxx xxxxxxxx mb91319 series 37 (continued) address register block + 0 + 1 + 2 + 3 078040 h osd_plt2 [w] xxxxxxxx xxxxxxxx osd_plt3 [w] xxxxxxxx xxxxxxxx osdc (main) 078044 h osd_plt4 [w] xxxxxxxx xxxxxxxx osd_plt5 [w] xxxxxxxx xxxxxxxx 078048 h osd_plt6 [w] xxxxxxxx xxxxxxxx osd_plt7 [w] xxxxxxxx xxxxxxxx 07804c h osd_plt8 [w] xxxxxxxx xxxxxxxx osd_plt9 [w] xxxxxxxx xxxxxxxx 078050 h osd_plt10 [w] xxxxxxxx xxxxxxxx osd_plt11 [w] xxxxxxxx xxxxxxxx 078054 h osd_plt12 [w] xxxxxxxx xxxxxxxx osd_plt13 [w] xxxxxxxx xxxxxxxx 078058 h osd_plt14 [w] xxxxxxxx xxxxxxxx osd_plt15 [w] xxxxxxxx xxxxxxxx 07805c h osd_act1 [w] xxxxxxxx xxxxxxxx osd_act2 [w] xxxxxxxx xxxxxxxx 078060 h osd_placc11 [w] xxxxxxxx xxxxxxxx osd_placc12 [w] xxxxxxxx xxxxxxxx 078064 h osd_placc2 [w] xxxxxxxx xxxxxxxx osd_placc3 [w] xxxxxxxx xxxxxxxx 078068 h osd_plbcc11 [w] xxxxxxxx xxxxxxxx osd_plbcc12 [w] xxxxxxxx xxxxxxxx 07806c h osd_plbcc2 [w] xxxxxxxx xxxxxxxx osd_plbcc3 [w] xxxxxxxx xxxxxxxx 078070 h osd_plcc11[w] xxxxxxxx xxxxxxxx osd_plcc12[w] xxxxxxxx xxxxxxxx 078074 h osd_plcc2[w] xxxxxxxx xxxxxxxx osd_plcc3[w] xxxxxxxx xxxxxxxx 078078 h osd_csc1 [w] xxxxxxxx xxxxxxxx osd_csc2 [w] xxxxxxxx xxxxxxxx 07807c h to 0780ff h ?? 078100 h ccosd_vadr [w] xxxxxxxx xxxxxxxx ccosd_cd1 [w] xxxxxxxx xxxxxxxx osdc (cc) 078104 h ccosd_cd2 [w] xxxxxxxx xxxxxxxx ccosd_rcd1 [w] xxxxxxxx xxxxxxxx 078108 h ccosd_rcd2 [w] xxxxxxxx xxxxxxxx ccosd_soc1 [w] xxxxxxxx 0000xxxx 07810c h ccosd_soc2 [w] xxxxxxxx xxxxxxxx ccosd_vdpc [w] xxxxxxxx xxxxxxxx mb91319 series 38 (continued) address register block + 0 + 1 + 2 + 3 078110 h ccosd_hdpc [w] xxxxxxxx xxxxxxxx ccosd_cvsc [w] xxxxxxxx xxxxxxxx osdc (cc) 078114 h ? ccosd_thcc [w] xxxxxxxx xxxxxxxx 078118 h ?? 07811c h ?? 078120 h ?? 078124 h ?? 078128 h ?? 07812c h ?? 078130 h ? ccosd_dpc1 [w] xxxxxxxx xxxxxxxx 078134 h ccosd_dpc2 [w] xxxxxxxx xxxxxxxx ccosd_dpc3 [w] xxxxxxxx xxxxxxxx 078138 h ccosd_dpc4 [w] xxxxxxxx xxxxxxxx ccosd_irc [w] xxxxxxxx xxxxxxxx 07813c h ccosd_plt0 [w] xxxxxxxx xxxxxxxx ccosd_plt1 [w] xxxxxxxx xxxxxxxx 078140 h ccosd_plt2 [w] xxxxxxxx xxxxxxxx ccosd_plt3 [w] xxxxxxxx xxxxxxxx 078144 h ccosd_plt4 [w] xxxxxxxx xxxxxxxx ccosd_plt5 [w] xxxxxxxx xxxxxxxx 078148 h ccosd_plt6 [w] xxxxxxxx xxxxxxxx ccosd_plt7 [w] xxxxxxxx xxxxxxxx 07814c h ccosd_plt8 [w] xxxxxxxx xxxxxxxx ccosd_plt9 [w] xxxxxxxx xxxxxxxx 078150 h ccosd_plt10 [w] xxxxxxxx xxxxxxxx ccosd_plt11 [w] xxxxxxxx xxxxxxxx 078154 h ccosd_plt12 [w] xxxxxxxx xxxxxxxx ccosd_plt13 [w] xxxxxxxx xxxxxxxx 078158 h ccosd_plt14 [w] xxxxxxxx xxxxxxxx ccosd_plt15 [w] xxxxxxxx xxxxxxxx 07815c h ?? 078160 h to 07ffff h reserved reserved mb91319 series 39 interrupt factors, interrupt ve ctors, and interrupt register (continued) interrupt factor interrupt number interrupt level offset address of tbr default rn decimal hexa- decimal reset 0 00 ? 3fc h 000ffffc h ? mode vector 1 01 ? 3f8 h 000ffff8 h ? system reserved 2 02 ? 3f4 h 000ffff4 h ? system reserved 3 03 ? 3f0 h 000ffff0 h ? system reserved 4 04 ? 3ec h 000fffec h ? system reserved 5 05 ? 3e8 h 000fffe8 h ? system reserved 6 06 ? 3e4 h 000fffe4 h ? coprocessor absent trap 7 07 ? 3e0 h 000fffe0 h ? coprocessor error trap 8 08 ? 3dc h 000fffdc h ? inte instruction 9 09 ? 3d8 h 000fffd8 h ? instruction break exception 10 0a ? 3d4 h 000fffd4 h ? operand break trap 11 0b ? 3d0 h 000fffd0 h ? step trace trap 12 0c ? 3cc h 000fffcc h ? nmi request (tool) 13 0d ? 3c8 h 000fffc8 h ? undefined instruction exception 14 0e ? 3c4 h 000fffc4 h ? nmi request 15 0f 15 (f h ) fixed 3c0 h 000fffc0 h ? external interrupt 0 16 10 icr00 3bc h 000fffbc h ? external interrupt 1 17 11 icr01 3b8 h 000fffb8 h ? external interrupt 2 18 12 icr02 3b4 h 000fffb4 h ? external interrupt 3 19 13 icr03 3b0 h 000fffb0 h ? external interrupt 4 (usb function) 20 14 icr04 3ac h 000fffac h ? external interrupt 5 (osdc-main) 21 15 icr05 3a8 h 000fffa8 h ? external interrupt 6 (osdc-cc) 22 16 icr06 3a4 h 000fffa4 h ? system reserved 23 17 icr07 3a0 h 000fffa0 h ? reload timer 0 24 18 icr08 39c h 000fff9c h 8 reload timer 1 25 19 icr09 398 h 000fff98 h 9 reload timer 2 26 1a icr10 394 h 000fff94 h 10 uart0 (reception comp leted) 27 1b icr11 390 h 000fff90 h 0 uart1 (reception completed) 28 1c icr12 38c h 000fff8c h 1 uart2 (reception completed) 29 1d icr13 388 h 000fff88 h 2 uart0 (transmission completed) 30 1e icr14 384 h 000fff84 h 3 uart1 (transmission completed) 31 1f icr15 380 h 000fff80 h 4 mb91319 series 40 (continued) interrupt factor interrupt number interrupt level offset address of tbr default rn decimal hexa- decimal uart2 (transmission completed) 32 20 icr16 37c h 000fff7c h 5 dmac0 (end, error) 33 21 icr17 378 h 000fff78 h ? dmac1 (end, error) 34 22 icr18 374 h 000fff74 h ? dmac2 (end, error) 35 23 icr19 370 h 000fff70 h ? dmac3 (end, error) 36 24 icr20 36c h 000fff6c h ? dmac4 (end, error) 37 25 icr21 368 h 000fff68 h ? a/d 38 26 icr22 364 h 000fff64 h ? ppg0 39 27 icr23 360 h 000fff60 h ? ppg1 40 28 icr24 35c h 000fff5c h ? ppg2 41 29 icr25 358 h 000fff58 h ? ppg3 42 2a icr26 354 h 000fff54 h ? pwc 43 2b icr27 350 h 000fff50 h ? ccd0 44 2c icr28 34c h 000fff4c h ? ccd1 45 2d icr29 348 h 000fff48 h ? main oscillation wait 46 2e icr30 344 h 000fff44 h ? timebase timer overflow 47 2f icr31 340 h 000fff40 h ? system reserved 48 30 icr32 33c h 000fff3c h ? watch timer 49 31 icr33 338 h 000fff38 h ? i 2 c ch0 50 32 icr34 334 h 000fff34 h ? i 2 c ch1 51 33 icr35 330 h 000fff30 h ? i 2 c ch2 52 34 icr36 32c h 000fff2c h ? i 2 c ch3 53 35 icr37 328 h 000fff28 h ? uart3 (reception completed) 54 36 icr38 324 h 000fff24 h ? uart4 (reception completed) 55 37 icr39 320 h 000fff20 h ? uart3 (transmission completed) 56 38 icr40 31c h 000fff1c h ? uart4 (reception completed) 57 39 icr41 318 h 000fff18 h ? multi-functional timer 0 58 3a icr42 314 h 000fff14 h ? multi-functional timer 1 59 3b icr43 310 h 000fff10 h ? multi-functional timer 2 60 3c icr44 30c h 000fff0c h ? multi-functional timer 3 61 3d icr45 308 h 000fff08 h ? system reserved 62 3e icr46 304 h 000fff04 h ? delay interrupt factor bit 63 3f icr47 300 h 000fff00 h ? system reserved (used by realos) 64 40 ? 2fc h 000ffefc h ? system reserved (used by realos) 65 41 ? 2f8 h 000ffef8 h ? mb91319 series 41 (continued) interrupt factor interrupt number interrupt level offset address of tbr default rn decimal hexa- decimal system reserved 66 42 ? 2f4 h 000ffef4 h ? system reserved 67 43 ? 2f0 h 000ffef0 h ? system reserved 68 44 ? 2ec h 000ffeec h ? system reserved 69 45 ? 2e8 h 000ffee8 h ? system reserved 70 46 ? 2e4 h 000ffee4 h ? system reserved 71 47 ? 2e0 h 000ffee0 h ? system reserved 72 48 ? 2dc h 000ffedc h ? system reserved 73 49 ? 2d8 h 000ffed8 h ? system reserved 74 4a ? 2d4 h 000ffed4 h ? system reserved 75 4b ? 2d0 h 000ffed0 h ? system reserved 76 4c ? 2cc h 000ffecc h ? system reserved 77 4d ? 2c8 h 000ffec8 h ? system reserved 78 4e ? 2c4 h 000ffec4 h ? system reserved 79 4f ? 2c0 h 000ffec0 h ? used by int instruction 80 to 255 50 to ff ? 2bc h to 000 h 000ffebc h to 000ffc00 h ? mb91319 series 42 electrical characteristics 1. absolute maximum ratings * : the parameter is based on v ss = 0 v. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. 2. recommended operating conditions (v ss = 0 v) warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may advers ely affect reliability and coul d result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their representatives beforehand. parameter symbol rating unit remarks min max power supply voltage * v dde (3.3 v) v ss ? 0.5 v ss + 4.0 v v ddi (2.5 v) v ss ? 0.5 v ss + 3.0 v analog power supply voltage * av cc v ss ? 0.5 v ss + 4.0 v input voltage * v i v ss ? 0.5 v dde + 0.5 v analog pin input voltage * v ia v ss ? 0.5 avcc + 0.5 v output voltage * v o v ss ? 0.5 v dde + 0.5 v storage temperature tstg ? 40 + 125 c parameter symbol value unit remarks min max operating temperature ta ? 40 + 70 c power supply voltage v dde (3.3 v) 3.00 3.6 v v ddi (2.5 v) 2.30 2.70 analog power supply voltage av cc 3.00 v dde v mb91319 series 43 3. dc characteristics (1) cpu (ta = ? 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, v ss = 0 v) (continued) parameter sym bol conditions value unit remarks min typ max power supply current i cct watch mode ta = + 25 c, fclk = 32 khz ? 800 1300 a dot clock pll stop usb clock stop i cc rom product normal operation ta = + 25 c, fcp = 40 mhz, fcpp = 20 mhz ? 240 280 ma font mask rom dot clock at 90 mhz i ccs main sleep mode ta = + 25 c, fcp = 40 mhz, fcpp = 20 mhz ? 160 200 ma dot clock pll stop i ccl sub run mode ta = + 25 c, fclk = 32 khz ? 1000 1700 a dot clock pll stop usb clock stop i cch main stop mode ta = + 25 c, fclk = 0 khz ? 150 400 a font mask rom main stop mode ta = + 70 c, fclk = 0 khz ? 1200 4000 a font mask rom ?h? level input voltage v ih ? v cc 0.8 ? v cc v ?l? level input voltage v il v cc = 3.3 v v ss ? v cc 0.2 v p00 to p74, pa0 to pa2, pb0 to pb7, pc0 to pc7, dcki, hsync1 to hsync3, vsync v cc = 2.5 v v cc 0.15 v b0 to b2, g0 to g2, r0 to r2, vob1, vob2, dcko, fh ?h? level output voltage v oh v cc = 3.3 v, i oh = ? 4 ma v cc ? 0.5 ? v cc vp0 to pc v cc = 2.5 v, i oh = ? 4 ma v b0 to b2, g0 to g2, r0 to r2, vob1, vob2, dcko, fh ?l? level output voltage v ol v cc = 3.3 v, i ol = 4 ma v ss ? 0.4 vp0 to pc v cc = 2.5 v, i ol = 4 ma v b0 to b2, g0 to g2, r0 to r2, vob1, vob2, dcko, fh input leak current i il ? ? 5 ? 5 a i 2 c bus switch connection resistance r bs ??? 130 between scl2 and scl3 between sda2 and sda3 between scl3 and scl4 between sda3 and sda4 mb91319 series 44 (continued) parameter sym bol conditions value unit remarks min typ max analog rgb reference voltage v ref ? 1.05 1.10 1.15 v vref analog rgb reference resistance r ref ? 2.4 2.7 ? k between vr0 and gnd analog rgb output impedance r l ?? 150 160 rout, gout, bout mb91319 series 45 (2) usb ? dc characteristics (1) (ta = ? 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, v ss = 0 v) *1 : about the output short-circuit current i os output short-circuit current i os is the maximum current that flows when the output pin is connected to v dde or v ss (within the maximum rating) . about the output short-circuit current : the current is ?the short-circuit current per differential output pin?. as the usb i/o buffer is a differential output, the short-circuit current should be considered for both of the output pins. parameter symbol pin conditions value unit remarks min typ max ?h? level output voltage v oh ? i oh = ? 100 av dde ? 0.2 ? v dde v ?l? level output voltage v ol ? i ol = 100 a0 ? 0.2 v ?h? level output current i oh ? at full speed mode v oh = v dde ? 0.4 v ? 20 ?? ma at low speed mode v oh = v dde ? 0.4 v ? 6 ?? ma ?l? level output current i ol ? at full speed mode v ol = 0.4 v 20 ?? ma at low speed mode v ol = 0.4 v 6 ?? ma output short- circuit current i os ?? ?? 300 ma *1 input leak current i lz ?? ?? 5 a*2 ?h? level ?l? level ?h? output ? l ? output monitor the short-circuit current short-circuited at gnd level short-circuited at v dde level monitor the short-circuit current 3-state enable ?l? 3-state enable ?l? mb91319 series 46 *2 : about measurement of ?z? leakage currrent i lz input leakage current i lz is measured with the usb i/o buffer in the high-impedance state when the v dde or v ss voltage is applied to the bidirectional pin. ?z? output monitor the leakage current 0 v and v dd level applied to output pin 3-state enable ?h? mb91319 series 47 ? dc characteristics (2) conform to the usb specification revision 1.1. (ta = ? 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, v ss = 0 v) *1 : about input voltage v ih , v il the switching threshold voltage of the usb i/o buffer?s single-end receiver is set within the range from v il (max) = 0.8 v to v ih (min) = 2.0 v (ttl input standard) . for v ih and v il , the lsi has some hysteresis to reduce noise susceptibility. *2 : about input voltage v di , v cm a differential receiver is used to receive usb differential data signals. the differential receiver has a differential input sensitivit y of 200 mv when the differential data input falls within the range from 0.8 v to 2.5 v with respect to the local ground reference level. the above voltage range is referred to as common-mode input voltage range. parameter symbol value unit remarks min max input voltage : high (driven) v ih 2.0 ? v*1 low v il ? 0.8 v *1 differential input sensitivity v di 0.2 ? v*2 common mode input voltage v cm 0.8 2.5 v *2 output voltage : low v ol 0.0 0.3 v *3 high (driven) v oh 2.8 3.6 v *3 output signal crossover voltage v crs 1.3 2.0 v *4 terminations : pull-up resistor on upstream port r pu 1.425 1.575 k 1.5 k 5 % pull-down resistor on downstream port r pd 1.425 1.575 k 1.5 k 5 % termination voltage for upstream port pull-up v term 3.0 3.6 v *5 0.8 0.2 1.0 2.5 common mode input voltage (v) minimum operating input sensitivity (v) mb91319 series 48 *3 : about output voltage v ol , v oh the output driving performance levels of the driver are 0.3 v or less (to 3.6 v, 1.5 k load) in the low state (v ol ) and 2.8 v or more (to ground, 1.5 k load) in the high state (v oh ) . *4 : about output voltage v crs the cross voltage of the external differential output signals (d + and d ? ) for the usb i/o buffer falls within the range from 1.3 v to 2.0 v. *5 : about terminations v term v term indicates the pull-up voltage at the upstream port. d + max 2.0 (v) max 1.3 (v) d ? v crs standard range mb91319 series 49 4. ac characteristics (1) clock timing (ta = ? 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, v ss = 0 v) * : the numeric value when inputting th e 6.25 mhz (the minimum clock freque ncy) to x0 and using the pll system and the gear rati o 1/16 of the oscillator circuit. (2) reset input (ta = ? 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, v ss = 0 v) note: t cp is the internal clock time. see ?(1) clock timing?. parameter symbol pin conditions value unit remarks min max clock frequency f c x0, x1 ? 6.25 10 mhz pll system (operation at a maximum internal speed of 40 mhz by quadrupling a self-oscillation frequency of 10 mhz via pll) internal operating clock frequency f cp ?? 1.56* 40 mhz cpu system (t cp = 1/f cp ) f cpp 1.56* 20 mhz peripheral system (t cpp = 1/f cpp ) f cpt 1.56* 20 mhz external bus system (t cpt = 1/f cpt ) parameter symbol pin conditions value unit remarks min max init input time (at power-on) t intl init ? oscillation stabilization wait time of oscillator + t cp 10 ? s init input time (other than at power-on) t cp 10 ? ns init input time (at recovering stop) oscillation stabilization wait time of oscillator + t cp 10 ? s init 0.2 v cc t rstl , t intl mb91319 series 50 (3) uart timing (ta = ? 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, v ss = 0 v) note : ? t cpp indicates the peripheral clock cycle time. see ?(1) clock timing?. ? ac rating in clk synchronous mode. parameter symbol pin conditions value unit remarks min max serial clock cycle time t scyc sck0 to sck4 internal shift lock mode 8 t cpp ? ns sck so delay time t slov sck0 to sck4, so0 to so4 ? 80 80 ns valid sin sck t ivsh sck0 to sck4, si0 to si4 100 ? ns sck valid si hold time t shix sck0 to sck4, si0 to si4 60 ? ns serial clock ?h? pulse width t shsl sck0 to sck4 external shift lock mode 4 t cpp ? ns serial clock ?l? pulse width t slsh sck0 to sck4 4 t cpp ? ns sck so delay time t slov sck0 to sck4, so0 to so4 ? 150 ns valid si sck t ivsh sck0 to sck4, si0 to si4 60 ? ns valid sck valid si hold time t shix sck0 to sck4, si0 to si4 60 ? ns ? internal shift clock mode ? external shift clock mode sck0 to sck4 so0 to so4 si0 to si4 t scyc t slov t ivsh t shix v ol v oh v ol v oh v ol v oh v ol v oh v ol sck0 to sck4 so0 to so4 si0 to si4 t slov t slsh t shsl t ivsh t shix v oh v ol v oh v oh v oh v oh v oh v ol v oh v ol mb91319 series 51 (4) reload timer clock , ppg timer i nput, multi-functional timer input timing (ta = ? 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, v ss = 0 v) note : t cpp indicates the peripheral clock cycle time. see ?(1) clock timing?. (5) trigger input timing (ta = ? 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, v ss = 0 v) note : t cpp indicates the peripheral clock cycle time. see ?(1) clock timing?. parameter symbol pin conditions value unit remarks min max input pulse width t tiwh t tiwl tin0 to tin2, ppg0 to ppg3, trg0 to trg3, tmi0 to tmi3 ? 2 t cpp ? ns parameter symbol pin conditions value unit remarks min max a/d activation trigger input time t atgx atg ? 5 t cpp ? ns t tiwh t tiwl atg t atgx mb91319 series 52 (6) usb interface (ta = ? 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, v ss = 0 v) *1 : the ac characteristics of the usb interface conform to usb specification revision 1.1. *2 : about driver characteristics t utfr , t utff , t utfrfm these items specify the differential data signal rise (rise time) and fall (fall time) times. these are defined as the times between 10 % to 90 % of the output signal voltage. for the full-speed buffer, t utfr and t utff are specified such that the t utfr /t utff ratio falls within 10 % to minimize rfi radiation. parameter symbol pin conditions value unit remarks min typ max input clock t ucyc x0b, x1b ? ? 48* 1 ? mhz self-oscillation 500 ppm accuracy * 1 x0b ? external input 500 ppm accuracy * 1 rise time t utfr udp/ udm at full speed mode 4 ? 20 ns *2 fall time t utff udp/ udm at full speed mode 4 ? 20 ns *2 differential rise and fall timing matching t utfrfm udp/ udm at full speed mode 90 ? 111.11 % *2 driver output resistance t zdrv udp, udm ? 28 ? 44 *3 x0b (x1b) t ucyc 10% 10% 90% 90% udp udm t utfr t utff mb91319 series 53 *3 : about driver characteristics zdrv usb full-speed connection is performed via a shielded twisted-pair cable at a characteristic impedance of 90 15 % . the usb standard stipulates that the usb driver?s output impedance must be within the range of 28 to 44 . the usb standard also stipulates that a discrete serial resistor (rs) must be added to have balance while satisfying the above standard. the output impedance of the usb i/o buffer on this lsi is about 3 to 19 . therefore, serial resistor r s to be added must be 25 to 30 (27 recommended) . t d + t d ? 3-state rs rs 28 to 44 equiv. imped 28 to 44 equiv. imped driver output impedance 3 to 19 rs serial resistance: 25 to 30 add a serial resistor of preferably 27 mb91319 series 54 (7) analog rgb (ta = ? 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, v ss = 0 v) * : vro is an external resistor for dac. parameter symbol pin conditions value unit remarks min typ max analog rgb output delay t vad rout, gout, bout v ref = 1.1 v, v ddr = v ddg = v ddb = 2.5 v, vro* = 2.7 k ? 12 ? ns 50 mhz (max) analog rgb output settling time t vas rout, gout, bout ?? 20 ns ? display signal output timing rout gout bout dcki t vad 1 lsb 1 lsb t vas mb91319 series 55 (8) digital rgb vertical synchronous, horizontal synchronous, and display output control signal input timing (ta = ? 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, v ss = 0 v) *1 : during the horizontal sync signal pulse period, the device stops its internal osdc operation, disabling writing to the internal vram. therefore, set the horizontal sync signal pulse width and vram write cycle to ensure that : horizontal sync signal pulse width < vram write cycle. precisely, adjust the command issuance interval not to issue command 2 or command 4 (vram write command) more than twice in the horizontal sync signal pulse width period. if the above condition is not satisfied, the device may fail writing to vram. *2 : 1h is assumed to be one horizontal sync signal period. parameter symbol pin value unit remarks min max horizontal sync signal cycle time t hcyc hsync1 to hsync3 100 + t wh ? dot clock horizontal sync signal pulse width t wh hsync1 to hsync3 20 ? dot clock *1 ? 6 s horizontal sync signal setup time t dhst hsync1 to hsync3 4 ? ns horizontal sync signal hold time t dhhd 0 ? ns vertical sync signal setup time t hvst vsync 51h* 2 ? 5 dot clock vertical sync signal hold time t hvhd 3 ? h* 2 input sync signal rise/fall time t dr t df hsync1 to hsync3, vsync ? 2ns t dhst 0.8 v dd 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd 0.2 v dd t dr, t df t dhhd hsync1 to hsync3 dcki ? horizontal sync signal, display output control signal input timing mb91319 series 56 0.8 v dd 0.8 v dd 0.2 v dd t wh t hcyc 0.8 v dd 0.2 v dd t dr t df hsync1 to hsync3 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd t dr t df 0.8 v dd 0.2 v dd t wh t hvhd t hvst 0.8 v dd 0.2 v dd t dr t df hsync1 to hsync3 vsync 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd t dr t df 0.8 v dd 0.2 v dd t wh t hvhd t hvst 0.8 v dd 0.2 v dd t dr t df hsync1 to hsync3 vsync ? horizontal sync signal input ? vertical sync signal input timing ? vsync detection at the leading edge of hsync ? vsync detection at the trailing edge of hsync mb91319 series 57 (9) display signal timing (ta = ? 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, v ss = 0 v) *1 : input a continuous dot clock signal without a break. *2 : output load 16 pf note : the actual display output varies depending on how the display output/position is controlled for each display layer. parameter symbol pin value unit remarks min max dot clock cycle time t dif dcki 11 90 mhz *1 dot clock pulse time t diwh dcki 5 ? ns *1 t diwl 5 ? ns dot clock output delay time 1 t pdc dcko 3 8 ns *2 display signal output delay time i1 t pdi1 r0 to r2, b0 to b2, g0 to g2, vob1, vob2 28ns*2 display signal output delay time o1 t pdo1 r0 to r2, b0 to b2, g0 to g2, vob1, vob2 ? 45ns*2 ? display signal output timing dcki dcko r0 to r2 b0 to b2 g0 to g2 vob1, vob2 t pdcs t dif t diwh t diwl t pdo1 t pdi1 t pdc 0.8 v dd 0.8 v dd 0.2 v dd 0.2 v dd 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd mb91319 series 58 (10-a) external circuit for data slicer (ta = ? 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, v ss = 0 v) (10-b) external circuit for data slicer (ta = ? 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, v ss = 0 v) parameter symbol pin value unit remarks min typ max video signal input level v vin vin0, vin1 1.0 ? 1.5 vp-p parameter symbol pin value unit remarks min typ max coupling condenser for vin pin c vin vin0, vin1 ?? 0.1 f more than b features 10 % of error ceramic condenser resistor for clamp r cl vin0, vin1 ?? 1m 5 % of error input resistance for vin pin r in vin0, vin1 ?? 0 5 % of error condenser of lo w pass filter for vin c 1 ??? 82 pf more than b features 10 % of error ceramic condenser power supply bypass condenser c bp vddis, vsss ?? 0.1 f ceramic condenser resistance for video signal input buffer r 1 ??? 2.2 k 5 % of error video signal input level correcting resistor r 2 ??? 4.7 k 5 % of error video signal input level correcting resistor r 3 ?? 10 12 k 5 % of error mb91319 series 59 external recommended circuit for data slicer vsss vddis 2.5 v 5 v c bp c vin c 1 r in r 1 r 2 r 3 r cl vin0, vin1 composite video signal (2 vp-p) 2sb709a equivalent (1) when the input composite video signals have been dc clamped 10 k vsss vddis 2.5 v 5 v c bp c vin c 1 r in r 1 r 2 r 3 r cl vin0, vin1 composite video signal (2 vp-p) 2sb709a equivalent (5 % of error) add this resistor (2) when the input composite video signals have not been dc clamped mb91319 series 60 (11) i 2 c timing ? at master mode operating (ta = ? 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, v ss = 0 v) *1 : m = resource clock cycle (ns) *2 : a fast-mode i 2 c bus device can be used for a standard mode i 2 c bus system as long as the device satisfies a requirement of ?t sudat 250 ns?. when the device does not extend the ?l? period of the scl signal, the next data must be outputted to the sda line within 1250 ns (maximum sda/scl rise time + t sudat ) in which the scl line is released. *3 : for use at over 100 khz, set the resource clock to at least 6 mhz. *4 : r and c represent the pull-up resistor and load capacitor of the scl and sda output lines. parameter sym- bol conditions typical mode high-speed mode* 3 unit remarks min max min max scl clock frequency f scl r = 1 k c = 50 pf* 4 0 100 0 400 khz ?l? period of scl clock t low 4.7 ? 1.3 ? s ?h? period of scl clock t high 4.0 ? 0.6 ? s bus free time between [stop condition] and [start condition] t bus 4.7 ? 1.3 ? s scl sda output delay time t dldat ? 5 m* 1 ? 5 m* 1 ns setup time of [repeat start condition] scl sda t susta 4.7 ? 0.6 ? s hold time of [repeat start condition] sda scl t hdsta 4.0 ? 0.6 ? s after that, the first clock pulse is generated. setup time of [stop condition] scl sda t susto 4.0 ? 0.6 ? s sda data input hold time (vs. scl ) t hddat 2 m* 1 ? 2 m* 1 ? s sda data input setup time (vs. scl ) t sudat 250 ? 100* 2 ? ns mb91319 series 61 ? at slave mode operating (ta = ? 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = = 2.5 v 0.2 v, v ss = 0 v) *1 : m = resource clock cycle (ns) *2 : a fast-mode i 2 c bus device can be used for a standard mode i 2 c bus system as long as the device satisfies a requirement of ?t sudat 250 ns?. when the device does not extend the ?l? period of the scl signal, the next data must be outputted to the sda line within 1250 ns (maximum sda/scl rise time + t sudat ) in which the scl line is released. *3 : for use at over 100 khz, set the resource clock to at least 6 mhz. *4 : r and c represent the pull-up resistor and load capacitor of the scl and sda output lines. parameter sym- bol conditions typical mode high-speed mode* 3 unit remarks min max min max scl clock frequency f scl r = 1 k c = 50 pf* 4 0 100 0 400 khz ?l? period of scl clock t low 4.7 ? 1.3 ? s ?h? period of scl clock t high 4.0 ? 0.6 ? s scl sda output delay time t dldat ? 5 m* 1 ? 5 m* 1 ns bus free time between [stop condition and start condition] t bus 4.7 ? 1.3 ? s sda data input hold time (vs. scl ) t hddat 2 m* 1 ? 2 m* 1 ? s sda data input setup time (vs. scl ) t sudat 250 ? 100* 2 ? ns setup time of [repeat start condition] scl sda t susta 4.7 ? 0.6 ? s hold time of [repeat start condition] sda scl t hdsta 4.0 ? 0.6 ? s after that, the first clock pulse is generated. setup time of [stop condition] scl sda t susto 4.0 ? 0.6 ? s mb91319 series 62 5. 0.25 m technology about the power-on sequence for dual-power-supply models ? the power supplies must be turned on in the vddi avcc, avrh, vdde order and off in the vdde avcc, avrh, vddi order. 6. electrical characteristics for the a/d converter (ta = ? 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, v ss = 0 v, v sse = v ssi = av ss = 0 v, avrh = 3.0 v to 3.6 v) *1 : measured in the cpu sleep state *2 : depends on the clock cycle of the clock signal supplied to peripheral resources. parameter value unit remarks min typ max resolution ?? 10 bit total error* 1 ? 5.5 ? + 5.5 lsb av cc = 3.3 v, avrh = 3.3 v (at cpu sleep) nonlinear error* 1 ? 3.5 ? + 3.5 lsb differential linear error* 1 ? 2.0 ? + 2.0 lsb zero transition voltage* 1 ? 4.0 ? + 6.0 lsb full transition voltage* 1 avrh ? 5.5 ? avrh + 3.0 lsb conversion time 10* 2 ?? s power supply voltage (analog + digital) ? 3.6 ? ma ?? 5 a at stop converting reference power supply current (between avrh and avrl) ? 470 ? a avrh = 3.0 v, avrl = 0.0 v ?? 10 a at stop converting analog input capacitance ? 40 ? pf interchannel disparity ?? 4lsb mb91319 series 63 ? about the external impedance of the analog input and its sampling time ? a/d converter with sample and hold circuit. if the ex ternal impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sampling and hold capacitor is insufficient, adversely affecting a/d conversion precision. ? to satisfy the a/d conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. ? if the sampling time cannot be sufficient, connect a capacitor of about 0.1 f to the analog input pin. ? about errors ? as |avrh ? av ss | becomes smaller, values of relative errors grow larger. r c mb91f318a/mb91fv319a rc ? analog input circuit model analog input comparator during sampling : on 5 k (max) 40 pf (max) note : the values are reference values. 100 90 80 70 60 50 40 30 20 10 0 35 30 25 20 15 10 5 0 mb91f318a/mb91fv319a 0 1 2 34 5 6 7 8 0 2 4 6 8 10 12 14 16 18 20 mb91f318a/mb91fv319a ? the relationship between the external impedance and minimum sampling time minimum sampling time ( s) minimum sampling time ( s) external impedance (k ) external impedance (k ) [external impedance = 0 k to 100 k ] [external impedance = 0 k to 20 k ] mb91319 series 64 ordering information part number package remarks MB91FV319APMT-ES 176-pin plastic lqfp (fpt-176p-m07) for developing tool mb91319 series 65 package dimension 176-pin plastic lqfp (fpt-176p-m07) note 1) * : values do not include resin protrusion. resin protrusion is +0.25 (.010) max (each side) . note 2) pins width and pins thickness include plating thickness note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) . note : the values in parentheses are reference values. c 2004 fujitsu limited f176013s-c-1-1 details of "a" part 0?~8? 0.50?.20 (.020?008) 0.60?.15 (.024?006) 0.25(.010) (stand off) (.004?004) 0.10?.10 1.50 +0.20 0.10 +.008 .004 .059 (mounting height) 0.08(.003) (.006?002) 0.145?.055 "a" index 1 lead no. 44 45 88 89 132 133 176 0.50(.020) 0.22?.05 (.009?002) m 0.08(.003) *24.00?.10(.945?004)sq 26.00?.20(1.024?008)sq mb91319 series 66 memo mb91319 series 67 memo fujitsu microelectronics limited shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0722, japan tel: +81-3-5322-3347 fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ for further information please contact: north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ korea fujitsu microelectronics korea ltd. 206 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ asia pacific fujitsu microelectronics asia pte ltd. 151 lorong chuan, #05-08 new tech park, singapore 556741 tel: +65-6281-0770 fax: +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ fujitsu microelectronics shanghai co., ltd. rm.3102, bund center, no.222 yan an road(e), shanghai 200002, china tel: +86-21-6335-1560 fax: +86-21-6335-1605 http://cn.fujitsu.com/fmc/ fujitsu microelectronics pacific asia ltd. 10/f., world commerce centre, 11 canton road tsimshatsui, kowloon hong kong tel: +852-2377-0226 fax: +852-2376-3269 http://cn.fujitsu.com/fmc/tw all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representative s before ordering. the information, such as descri ptions of function and applicati on circuit examples, in this docum ent are presented solely for t he purpose of reference to show examples of ope rations and uses of fujits u microelectronics device; fujitsu microelectronics does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incor porat- ing the device based on such in formation, you must assume any responsibility arising out of such use of the information. fujitsu microelectronics assumes no liab ility for any damages whatsoever arisi ng out of the use of the information. any information in this document, including descriptions of function and schematic di agrams, shall not be construed as license of the use or exercise of any intellectual property ri ght, such as patent right or copyright, or any other right of fujitsu microelectroni cs or any third party or does fujitsu microel ectronics warrant non-infringeme nt of any third-party's intellectual property right o r other right by using such information. fu jitsu microelectronics assumes no liability for any infringement of the intellectual property rights or other rights of third parties which w ould result from the use of in formation cont ained herein. the products described in this document are designed, developed and manufa ctured as contemplated fo r general use, including wit hout limitation, ordinary indus trial use, general office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for use acco mpanying fatal risks or dangers th at, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead directly to death, personal injury, severe physical damage or other lo ss (i.e., nuc lear reaction control in nuclear facility, airc raft flight control, air traffic c ontrol, mass transport control, me dical life support system, missile la unch control in weapon system), or (2) for use requiring extremely high re liability (i.e ., submersible repeater and artificial satellite). please note that fujitsu microelectronics will not be liable against you and/or any th ird party for any clai ms or damages arisi ng in connection with above-men tioned uses of the products. any semiconductor devices have an inherent ch ance of failure. you must protect against injury, damage or loss from such failure s by incorporating safety desi gn measures into your facility and equipment such as redundancy, fire protection, and prevention of ov er-current levels and other abnor mal operating conditions. exportation/release of any products described in this docum ent may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand na mes herein are the trademarks or registered trademarks of their respective owners. edited strategic business development dept. |
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